1. Field of the Invention
Embodiments of the invention generally relate to the field of semiconductor manufacturing processes and devices, more particular, to methods of depositing silicon-containing films forming semiconductor devices.
2. Description of the Related Art
As smaller transistors are manufactured, ultra shallow source/drain junctions are becoming more challenging to produce. According to the International Technology Roadmap for Semiconductors (ITRS), junction depth is required to be less than 30 nm for sub-100 nm CMOS (complementary metal-oxide semiconductor) devices. Recently, selective SiGe epitaxy has become a useful material to deposit during formation of elevated source/drain and source/drain extension features. Source/drain extension features are manufactured by etching silicon to make a recessed source/drain feature and subsequently filling the etched surface with a selectively grown SiGe epilayer. Selective epitaxy permits near complete dopant activation with in-situ doping, so that the post annealing process is omitted. Therefore, junction depth can be defined accurately by silicon etching and selective epitaxy. On the other hand, the ultra shallow source/drain junction inevitably results in increased series resistance. Also, junction consumption during silicide formation increases the series resistance even further. In order to compensate for junction consumption, an elevated source/drain is epitaxially and selectively grown on the junction.
Selective Si-epitaxial deposition and SiGe-epitaxial deposition permits growth of epilayers on Si moats with no growth on dielectric areas. Selective epitaxy can be used in semiconductor devices, such as within elevated source/drains, source/drain extensions, contact plugs, and base layer deposition of bipolar devices. Generally, a selective epitaxy process involves two reactions: deposition and etch. The deposition and etch occur simultaneously with relatively different reaction rates on Si and on dielectric surface. A selective process window results in deposition only on Si surfaces by changing the concentration of an etchant gas (e.g., HCl).
Although SiGe-epitaxial deposition is suitable for small dimensions, this approach does not readily prepare doped SiGe, since the dopants react with HCl. The process development of heavily boron doped (e.g., higher than 5×1019 cm−3) selective SiGe-epitaxy is a much more complicated task because boron doping makes the process window for selective deposition narrow. Generally, when more boron concentration (e.g., B2H6) is added to the flow, a higher HCl concentration is necessary to achieve selectivity due to the increase growth rate of deposited film(s) on any dielectric areas. This higher HCl flow rate reduces boron incorporation into the epilayers presumably because the B—Cl bond is stronger than Ge—Cl and Si—Cl bonds.
Currently, there are two popular applications for selective silicon-based epitaxy in junction formation of silicon-containing MOSFET (metal oxide semiconductor field effect transistor) devices. One application is the process to deposit elevated source/drain (S/D) films by a selective epitaxy. Typically, this epitaxial layer is undoped silicon. Another application is filling of recessed junction areas with epitaxial silicon-containing films. Often, the silicon-based films contain germanium, carbon and/or a dopant.
MOSFET devices may contain a PMOS or a NMOS component, whereas the PMOS has a p-type channel, i.e., holes are responsible for conduction in the channel and the NMOS has an n-type channel, i.e., the electrons are responsible for conduction in the channel. For PMOS, the film in the recessed area is usually SiGe. For NMOS application, the film in the recessed area may be SiC. SiGe is used for PMOS application for several reasons. A SiGe material incorporates more boron than silicon alone, thus the junction resistivity is lowered. Also, the SiGe/silicide layer interface at the substrate surface has a lower Schottky barrier than the Si/silicide interface. Further, SiGe grown epitaxially on the top of silicon has compressive stress inside the film because the lattice constant of SiGe is larger than that of silicon. The compressive stress is transferred in the lateral dimension to create compressive strain in the PMOS channel and to increase mobility of the holes. For NMOS application, SiC can be used in the recessed areas to create tensile stress in the channel, since the lattice constant of SiC is smaller than that of silicon. The tensile stress is transferred into the channel and increases the electron mobility.
Therefore, there is a need to have a process for selectively and epitaxially depositing silicon and silicon-containing compounds with an enriched dopant concentration. Furthermore, the process should be versatile to form silicon-containing compounds with varied elemental concentrations.